ADV7280 + imx6ull输出图像问题

[yinkai]

采用ADV7280 + imx6ull，在调试CSI的时候，发现图像如下：

 

  图像的边界与显示的边界是错位的，图像有时分成两个或四个部分，并且图像变化时画面会滚动。

  软件使用v4l2框架，使用USERPTR，获取/dev/video1的图像，然后使用pxp将UYVY转换成RGB565显示在屏幕上。

1. ADV7280输入为PAL 30fps， interlace Mode，ADV7280 启用I2P， 输出为576p Progressive Mode。

      ADV7280的0x10寄存器的值为：0x4d，

2. IMX 6的主要配置为，启用CCIR，VideoMode为 Progressive Mode。

     主要寄存器的值如下：

       0x21c4000: 0x01190502

    0x21c4004: 0xC0000000

    0x21c4008: 0x79BA10A0

       0x21c4034: 0x05A00240

    0x21c4048: 0x8002D000

请问是什么原因造成的。

[hoanganh]

Hi Yin,

Can you sent me your mx6s_capture.c source code? I need that like an example

An i have problem with my understand

   - My camera always out put is bt.656, have 8 wire data and 1 wire clock. I think only "mx6s_capture.c" can capture data frame, no need "ADV7280".

   - I use uvc_streamer usb camera to pc over ethernet. Can use it to show video? If you not fell bothered, can you share me your app can see video like you first post. I'm very new member with NXP's chip and something is too hard to understand!

[joanxie · Accepted solution]

I got some hints from expert team about adv7280, hope helpful for you

"Some summary:

1. the adv7280 should be enabled after mipi_csi2_reset().

2. For MIPI CSI input, the clock mode in IPU_CSI_SENS_CONF must be gated clock mode.

          p->u.bt656.clock_curr = 1;

3. For interlaced input, IDMAC 0 should be set to interlaced mode: "params.csi_mem.interlaced = true;" For progressive input, IDMAC 0 shoudl be set to progressive mode: "params.csi_mem.interlaced = false;"

          case IPU_CSI_CLK_MODE_GATED_CLK: in file drivers\media\video\mxc\capture\ipu_csi_enc.c, function csi_enc_setup().

4. For device type:

     adv7280_data.sen.pix.priv = 1;  /* 1 is used to indicate TV in */"