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T1042 DDR Controller query!!

Question asked by Faiz Majeed on Oct 30, 2017
Latest reply on Oct 31, 2017 by Serguei Podiatchev

Hi i am using T1042 processor and i am trying to interface SDRAM with DDR Memory Controller. The reference manual mentions that the memory controller is receiving a 40 bit address from "core master" that is being converted to a 16 bit address later on. Can anyone please elaborate what is a core master?

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