Bit Manipulation Engine 2 (BME)
In Section 18.104.22.168 (Decorated Load: Load-and-Set 1 Bit (LAS1)) of the detailed KV58 spec (KV5XP144M240RM.pdf), the document describes that the base address for accessing (LAS1s) SRAM_U is 0x2000_0000.
This section is the only one where I see SRAM_U mentioned.
Does the SRAM_U region exist in the KV58 memory map?
If yes, then what is the memory range or how can SRAM_U be accessed?
In the K10/K20, SRAM_U refers to the Upper SRAM bitband region (0x2000_0000 to 0x200F_FFFF).
However the KV58 has Data SRAM (DTCM0 and 1) allocated between 0x2000_0000 and 0x2001_FFFF.
Does this mean that the upper DATA SRAM (DTCM1?) can be bit-banded?