I am using T1042 processor and trying to interface 3 NOR Flashes with IFC.
1 for booting
2 application flashes
i have select "Mode 0 pin muxing (CSORn[ADM_SHFT_MODE] = 0)" and have some confusion about address shifting scheme. and i am using nor flash which uses (A0 to A26) addresses.
i have three queries about using this all
1) what value should i select in CSORn[ADM_SHFT] register
2) what value should be selected in Reset configuration word (RCW) [cfg_rcw_src _[1:4]_[5:8]
3) which pins can i use for write protect for each chip select
4) which pins can i use for ready/busy
i am really confused in shifting mechanism of above mentioned two registers.
Do you have any suggestion ??