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Is it possible to achieve TRM mentioned data rate in MIPI CSI ?

Question asked by Titus Stalin on Oct 26, 2017
Latest reply on Oct 27, 2017 by Titus Stalin


I have interfaced our 4 lane supported camera into i.MX6 board and written our own camera driver based on i.MX6 reference camera OV5640 driver.

TRM mentioned that MIPI CSI2 supports data rate upto 800Mbps per lane when we use 4 lane configuration and 1Gbps/lane when we use 1/2/3 lane count.

IMX6DQRM.pdf, page no 450.


One MIPI/CSI-2 port- IPU receives two components per cycle from the MIPI_CSI2
interface. The maximum bandwidth of the interface is as follows:
• 400MByte/sec for four data lanes configuration (800Mbps/lane)
• 375MByte/sec for 3 data lanes configuration (1000Mbps/lane)
• 250MByte/sec for 2 data lanes configuration (1000Mbps/lane)
• 125Mbyte/sec for 1 data lanes configuration (1000Mbps/lane)


I can achieve 1Gbps/lane for 1/2/3 lane configurations as mentioned in TRM but unable to achieve 800Mbps/lane for 4 lane configuration, we are able to get 790Mbps/lane.

If we increase the CSI camera clock from 395MHz to 400MHz to support 800Mbps/lane, we are getting distorted frames.

So we wanted to know that really we can achieve the mentioned data rate for 4 lanes or its just based on theoritical calculation.

Thanks for your support.