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I.MX6Q black screen after power up

Question asked by Olaf Bähring on Oct 25, 2017
Latest reply on Nov 2, 2017 by Olaf Bähring

We are using u-boot and VxWorks7 on a iMX6 Q or DL processor. As display we use a screen either connected to HDMI or LVDS at a resolution of 1376x768. The display works fine when the processor is cold.
When the board is at normal temperature and a power off/on cycle is done, sometimes u-boot and the application is running, but the display keeps black in u-boot and/or in kernel. In some cases u-boot produces a splash screen, but the kernel GUI fails. In this case the IPU VSYNC irq 38 is missing.
When checking the IPU registers in error case of u-boot, we found, that some registers look different:

 

                                          good    failing
IPU1_SRM_PRI2.DP_S_SRM_MODE                    0        1
IPU1_DP_COM_CONF_SYNC.DP_GWAM_SYNC            0        1
IPU1_DP_Graph_Wind_CTRL_SYNC.DP_GWAV_SYNC    0        80
IPU1_DC_STAT.DC_TRIPLE_BUF_CNT_FULL_0       1       0
IPU1_DC_STAT.DC_TRIPLE_BUF_CNT_EMPTY_0      0       1
IPU1_DC_STAT.DC_TRIPLE_BUF_DATA_FULL_0      1       0
IPU1_DC_STAT.DC_TRIPLE_BUF_DATA_EMPTY_0     0       1
IPU1_DMFC_STAT.DMFC_FIFO_EMPTY_i  i=6       0       1

 

It seems, that no frames are generated and the IPU is not working at all. What can couse this misbehaviour ? Where should I have a look to ? The configuration is always thee same.

 

good case:
pixclock = 75386000l Hz
panel size = 1376 x 768
pixel clk = 75386000
setup_disp_channel2: 95ffcff 1376 768 2752 8d5918a0 8d7958a0
bpp_to_pixfmt: 16
initializing idma ch 23 @ 027005c0
IPU DMFC DP HIGH RES: 1(0,1), 5B(2~5), 5F(6,7)
ch 23 word 0 - 00000000 00000000 00000000 E0001800 000BFCAB
ch 23 word 1 - 91AF2B14 02356462 20E3C000 F2C2AFC0 00082CA0
PFS 0x7, BPP 0x3, NPB 0xf
FW 1375, FH 767, Stride 2751
Width0 4+1, Width1 5+1, Width2 4+1, Width3 7+1, Offset0 0, Offset1 5, Offset2 11, Offset3 16
clk_enable pixel_clk usecount 0
IPU_CONF =      0x00000660
IDMAC_CONF =    0x0000002F
IDMAC_CHA_EN1 =         0x00800000
IDMAC_CHA_EN2 =         0x00000000
IDMAC_CHA_PRI1 =        0x18800000
IDMAC_CHA_PRI2 =        0x00000000
IPU_CHA_DB_MODE_SEL0 =  0x00800000
IPU_CHA_DB_MODE_SEL1 =  0x00000000
DMFC_WR_CHAN =          0x00000090
DMFC_WR_CHAN_DEF =      0x202020F6
DMFC_DP_CHAN =          0x0000968A
DMFC_DP_CHAN_DEF =      0x2020F6F6
DMFC_IC_CTRL =          0x00000002
IPU_FS_PROC_FLOW1 =     0x00000000
IPU_FS_PROC_FLOW2 =     0x00000000
IPU_FS_PROC_FLOW3 =     0x00000000
IPU_FS_DISP_FLOW1 =     0x00000000
IPU_INT_STAT[0] =       0x00800000
IPU_INT_STAT[1] =       0x00000000
IPU_INT_STAT[2] =       0x00800000
IPU_INT_STAT[3] =       0x00000000
IPU_INT_STAT[4] =       0x00000000
IPU_INT_STAT[5] =       0x00000000
IPU_INT_STAT[6] =       0x00800000
IPU_INT_STAT[7] =       0x00000000
IPU_INT_STAT[8] =       0x00000000
IPU_INT_STAT[9] =       0x00000000
IPU_INT_STAT[10] =      0x00000000
IPU_INT_STAT[11] =      0x00000000
IPU_INT_STAT[12] =      0x00800000
IPU_INT_STAT[13] =      0x00000000
IPU_INT_STAT[14] =      0x00FF400C
IPU_SRM_PRI2 =          0x06050803
IPU_SRM_STAT =  0x00000000
IPU_TRIPLE_CUR_BUF_0 =  0x00000000
IPU_TRIPLE_CUR_BUF_1 =  0x00004000
IPU_PROC_TASKS_STAT =   0x00000000
IPU_DISP_TASKS_STAT =   0x00000000
IPU_DI0_GENERAL =       0x00300000
IPU_DI0_STAT =  0x00000001
IPU_DI1_GENERAL =       0x00200000
IPU_DI1_STAT =  0x00000005
IPU_DC_STAT =   0x000000A5
IPU_DMFC_GENERAL1 =     0x00000003
IPU_DMFC_GENERAL2 =     0x00000000
IPU_DMFC_STAT =         0x20200020
DI0 OK
Framebuffer at 0x8d5918a0

 


error case:
pixclock = 75386000l Hz
panel size = 1376 x 768
pixel clk = 75386000
setup_disp_channel2: 95ffcff 1376 768 2752 8d5918a0 8d7958a0
bpp_to_pixfmt: 16
initializing idma ch 23 @ 027005c0
IPU DMFC DP HIGH RES: 1(0,1), 5B(2~5), 5F(6,7)
ch 23 word 0 - 00000000 00000000 00000000 E0001800 000BFCAB
ch 23 word 1 - 91AF2B14 02356462 20E3C000 F2C2AFC0 00082CA0
PFS 0x7, BPP 0x3, NPB 0xf
FW 1375, FH 767, Stride 2751
Width0 4+1, Width1 5+1, Width2 4+1, Width3 7+1, Offset0 0, Offset1 5, Offset2 11, Offset3 16
IPU_CONF =      0x00000660
IDMAC_CONF =    0x0000002F
IDMAC_CHA_EN1 =         0x00800000
IDMAC_CHA_EN2 =         0x00000000
IDMAC_CHA_PRI1 =        0x18800000
IDMAC_CHA_PRI2 =        0x00000000
IPU_CHA_DB_MODE_SEL0 =  0x00800000
IPU_CHA_DB_MODE_SEL1 =  0x00000000
DMFC_WR_CHAN =          0x00000090
DMFC_WR_CHAN_DEF =      0x202020F6
DMFC_DP_CHAN =          0x0000968A
DMFC_DP_CHAN_DEF =      0x2020F6F6
DMFC_IC_CTRL =          0x00000002
IPU_FS_PROC_FLOW1 =     0x00000000
IPU_FS_PROC_FLOW2 =     0x00000000
IPU_FS_PROC_FLOW3 =     0x00000000
IPU_FS_DISP_FLOW1 =     0x00000000
IPU_INT_STAT[0] =       0x00000000
IPU_INT_STAT[1] =       0x00000000
IPU_INT_STAT[2] =       0x00000000
IPU_INT_STAT[3] =       0x00000000
IPU_INT_STAT[4] =       0x00000000
IPU_INT_STAT[5] =       0x00000000
IPU_INT_STAT[6] =       0x00000000
IPU_INT_STAT[7] =       0x00000000
IPU_INT_STAT[8] =       0x00000000
IPU_INT_STAT[9] =       0x00000000
IPU_INT_STAT[10] =      0x00000000
IPU_INT_STAT[11] =      0x00000000
IPU_INT_STAT[12] =      0x00000000
IPU_INT_STAT[13] =      0x00000000
IPU_INT_STAT[14] =      0x00000000
IPU_SRM_PRI2 =          0x0605080B
IPU_SRM_STAT =  0x00000000
IPU_TRIPLE_CUR_BUF_0 =  0x00000000
IPU_TRIPLE_CUR_BUF_1 =  0x00004000
IPU_PROC_TASKS_STAT =   0x00000000
IPU_DISP_TASKS_STAT =   0x00000000
IPU_DI0_GENERAL =       0x00300000
IPU_DI0_STAT =  0x00000001
IPU_DI1_GENERAL =       0x00200000
IPU_DI1_STAT =  0x00000005
IPU_DC_STAT =   0x000000AA
IPU_DMFC_GENERAL1 =     0x00000003
IPU_DMFC_GENERAL2 =     0x00000000
IPU_DMFC_STAT =         0x20200020
DI0 not working
Framebuffer at 0x8d5918a0

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