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IMX6S power-up sequence

Question asked by wayne_1 on Oct 24, 2017
Latest reply on Oct 24, 2017 by wayne_1

Hi all,

 

in our design VDDHIGH_IN and VDD_SNVS_IN of IMX6 Solo are supplied by VGEN4 of PMIC MMPF0100 (NP). VGEN4 (3V0) is supplied by PMIC SW2 (3V3) and this 3V3 is also supplying IMX6 GPIO voltages (NVCC_xxx). VGEN4 and SW2 are programmed to be the first in power-up sequence. Any problem here?

 

Many thanks!

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