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How to check the DDR access timing with JTAG?

Question asked by Tomokazu Miyazaki on Oct 23, 2017
Latest reply on Oct 24, 2017 by ufedor

I want to check DDR access timing of the LS1046A is correct with JTAG debugger.

The DDR validation tool seems to change the registers of CLK_ADJUST and WRLVL_START to determine whether the timing is correct, but can you do the same with JTAG?

I tried changing those registers with the JTAG debugger, but no matter what value I set, the access to the DDR memory did not become abnormal.

In order to check the setting value, can I only use the DDR validation tool?

 

Best regards,

tomo.

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