LPC43xx user guide UM10503 inconsistant

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I'm trying to get the ADC to trigger from ADCSTART1_IN using timer2 match 0. 

In the process I've noticed that the LPC43xx user guide (UM10503 rev 2.3) has errors.

CREG6 - Table 104, bit 4 = CTOUTCTRL

0 = Combine SCT and timer match outputs. SCTimer/PWM outputs are Red with timer outputs.
1 = SCTimer/PWM outputs only. SCTimer/PWM outputs are used without timer match outputs.

BTW the 'Red' should be 'ORed'.

GIMA 18.2 - To configure the GIMA inputs for the timers and SCT, set the CTOUTCTRL bit in CREG6 (Table 104). This bit controls whether the SCT outputs are ORed with the timer match outputs or whether the SCT outputs only are used.

Table 207 [1] To configure the GIMA inputs for the timers and SCT, set the CTOUTCTRL bit in CREG6 (Section 11.4.9). This bit controls whether the SCT outputs are ORed with the timer match output or whether the SCT outputs only are considered.

SCT 30.2 The SCT outputs are ORed with various timer match outputs if bit CTOUTCTRL in CREG6 is zero (see Table 104; this is the default). Set the CTOUTCTRL bit to one to use the SCT outputs without interference from the timers.

So in two instances the manuals says SCT & timer outputs are combined when CTOUTCTRL = 0, and in two instances the manual says they are combined when CTOUTCTRL = 1

In any case I can't get the ADCSTART1_IN to work yet.

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It works with CTOUTCTRL = 1

The problem I had with ADCSTART1_IN was two fold:

- ADC control register START needs to be 2 (depending on ADCSTART config)

- The ADC IRQ Handler clears the interrupt by reading the GDR

The last item got me.  The user manual states:

"Remark: Use only the individual channel data registers DR0 to DR7 with burst mode or with hardware triggering to read the conversion results."

And also:

"The result register of the A/D channel which is generating an interrupt must be read in order to clear the corresponding DONE flag"

So on that basis with hardware triggering I used the individual DR registers rather than the GDR. If you don't read the DGR to reset the DONE flag, then interrupts pile up and overflow the NVIC.  The manual should be annotated to state that reading DGR resets the DONE flag in hardware generated interrupts rather than reading the DR registers.  The last quote above from the manual is plain wrong.

[soledad]

Hi,

Thank you for your feedback, we will check the documentation,

Have a nice day!

Soledad

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