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What is the effect of using low differential reference voltage for S12X ATD?

Question asked by utwig on Oct 17, 2017
Latest reply on Oct 20, 2017 by utwig

I am using the ATD module on the MC9S12XEP100. My plan is to use +5.2 V for the MCU supplies (VDDA, VDDX etc.) and stable +5.0 V for the VRH ATD high voltage reference pin. This is to make sure that even if my +5.2 V source fluctuates, VRH will stay lower than VDDA, which is required for correct ATD operation.


I am expecting to measure voltages in the range of 1.5-4.5 V. I was thinking about providing stable +1.0 V for VRL ATD low reference voltage pin to make better use of the ATD dynamic range and improve the quantization resolution. From the Table A-15 in MC9S12XEP100 manual I see that using +1.0 V as VRL and +5.0 V as VRH is okay when VDDA is +5.2 V.


However Section A.2.2.1 states:

"The accuracy is reduced if the differential reference voltage is less than 3.13V when using the ATD in the3.3V range or if the differential reference voltage is less than 4.5V when using the ATD in the 5V range."


Is there any data available on how much the accuracy is reduced when using <4.5 V differential reference voltage (4.0 V in my case)? I would like to know if that penalty is greater than the benefit of the increased quantization resolution.