Basically, we have i.mx6sl ( MCIMX6L8DVN10AB ) and EDB8132B4PM-1D-F-D LPDDR2 memory and in this production run, we have found that an excessive percentage of boards are suffering from memory test failures. We found that if we adjust ZQPAD/ZQ resistor values, then this causes those boards to pass memory testing which indicates that there is a serious problem with DDR calibration. That indicates that the DDR trace impedance on the failing boards deviates from the 40 Ohm default that the SoC and LPDDR2 defaults to. As you can imagine, we can't fix that in hardware for this run so my understanding is that we need to change the drive strength/impedance values in software (changing both the SoC side drive values and the LPDDR2 side values) to accommodate this.
From experimentation on failing boards, we found that changing drive strength settings for GRP_B0DS and other pads in u-boot using imximage.cfg allows some boards to pass, but not others. On some boards, the lower chipselect addresses (512MB) pass, but not the upper.
Based on Where is MR3/ZQ calibration set up for mx6sl in u-boot or kernel? , we found that u-boot and the kernel do not setup MR3 (drive strength settings on the LPDDR2 side). u-boot has the code to do this in mx6_dram_cfg() but this function can't be called without enabling SPL. I tried adding the MMDC code bit by bit to dram_init() in regular u-boot but this hangs the moment I set MDSCR ( the equivalent of mmdc0->mdscr = (u32)(1 << 15); /* config request */ ).
I'm going to retry setting up CONFIG_SPL=y and CONFIG_SPL_BUILD, but in the meantime I wanted to ask:
- is there any way on 6sl to set the LPDDR2 MR3 register values in u-boot without needing to go to SPL?