I have a question about CSIx_SENS_PRTCL bit setteng, between Interlace and Progressive.
When, CSI set to input BT656 interlace like a section "2.1.1 BT.656 Interlace Setting" in
document i.MX6 IPU TVIN Application Note.
In this time, if CSIx_SENS_PRTCL bit change from 0x3(BT.656 interlaced mode)
to 0x2(BT.656 progressive mode), it can capture only field 0 line data because only
detect EAV/SAV pattern setting in IPU_CSI_CCIR_CODE_1 register.
And the IPU_CSI_CCIR_CODE_2 register setting is ignored.
Is it correct?