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mx6ull evk qspi NOR flash configuration is for Dual-SPI mode?

Question asked by DJ Regan on Oct 11, 2017
Latest reply on Oct 11, 2017 by DJ Regan

Hello,

 

This is sort-of a follow-up question from Question 950704https://community.nxp.com/message/950704

 

...specifically file: 'qspi-nor-micron-n25q256a-config' from NXP's Mfgtool2 (release 'L4.1.15_2.0.0-ga_mfg-tools') lists the proposed QSPI NOR flash header value for parameter Offset 64 (Mode of operation of serial Flash) as value '02'.

 

According to the table in the IMX6ULLRM (i.MX 6ULL Applications Processor Reference Manual, Rev. 0, 09/2016), value '02' on parameter Offset 64 means 'Dual' SPI mode. Is setting 'Dual' intentional? ...or... would it be better if this parameter value were to be revised to be value '04' for 'Quad' SPI mode operation?

 

File attachments...

'qspi-header.bin.zip' - NXP's default mx6ull evk QSPI nor flash config file (acquired from response to Question 950704).

'qspi-nor-micron-n25q256a-config' - ascii text file acquired from Mfgtool (release 'L4.1.15_2.0.0-ga_mfg-tools')

'qspi-nor-micron-n25q256a-config.dat.xlsx' - spreadsheet with imported Mfgtool config file, with indexed parameters showing expected hexadecimal byte offsets to each NOR flash configuration parameter.

 

Thoughts?

 

Thanks much in advance,

--DJ Regan

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