ADC multi ch with DMA on KL27

Discussion created by shuichiy on Oct 10, 2017

Hi, I'm now working on KL27Z256 with KSDK2.0.

My goal is to get 5ch data via ADC with DMA transfer.


I think 5*16bit ADC0-RA data should be stored in memory in a row, and ADC0->SC1 is switched automatically.

In my codes attached, only the first 16bit data is stored in memory even if ADC0->SC1 seems to be changed.


Unfortunately I haven't found any sample codes  on the SDK and here.

Is there something wrong ?

Your any advice will be appreciated.

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