i.MX6 FRC_MSR

[sugiyamatoshihi]

Hi, @TheAdmiral 

I have a question about FRC_MSR bit in MMDCx_MPMUR0 in DDR3 calibration.

Is it neccesarry to set  FRC_MSR in DCD with specific order?

I confused below description.

1. I think this bit doesn't need to set when HW caliibration is used according to description of this bit below in refference manual.  

NOTE: This bit should be used only during manual (SW) calibration and not while the DDR is functional
(being accessed). After initial calibration is done the hardware performs periodic measurements
to track any operating conditions changes. Hence, force measurements (FRC_MSR) should not
be used. See Calibration Process for more information.

2.However, you mentioned it is in ddr calibration script and described as below.

https://community.nxp.com/docs/DOC-94790?commentID=11319#comment-11319 

There is a specific order that the parameters must be loaded, and it the order is not followed, then the MMDC will have problems. In general, the order goes:

- IOMUX pin settings.

- MMDC Calibration settings, including ZQ calibration, followed by setting the FRC_MSR bit.

- Loading the main MMDC register settings (and initializing the MMDC by turning it on as the last register loaded in this section)

- Configuring the MR registers of the attached LPDDR2 devices.

3. Calibration script also described below.

// Complete calibration by forced measurement:
setmem /32 0x021b08b8 = 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr
setmem /32 0x021b48b8 = 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr

What will complete?

What function is FRC_MSR?

Best Regards,

Sugiyama

[TheAdmiral · Accepted solution]

Hi Sugiyama-san,

Let me first start by providing and overview:

For most all of the fields in the registers associated with the PHY (0x021B0800 - 0x021B08C0, and 0x021B4800 - 0x021B48C0 if applicable), the manual settings that you make in these registers do not actually take effect in the PHY until you set the frc_msr bit. This serves the practical purpose of allowing you to set all the registers as you want, and then affect the PHY with the changes all at once. The exceptions should be obvious (ZQ_HW_FOR, ZQ_SW_FOR, RST_RD_FIFO etc).

When the PHY makes register changes as a result of a HW (automatic) initiated calibration, those register settings will be automatically pushed into the PHY as part of that action, so in this case, the frc_msr is not required.

The most common example of this is ZQ calibration. If the ZQ_HW_FOR bit is set to force a measurement of the ZQ calibration resistor, then the measured results (ZQ_HW_PD_RES, ZQ_HW_PU_RES) are not applied to the pads in the PHY until the frc_msr bit is set. But if ZQ_MODE 1 or 3 is selected and the ZQ_HW_PER counter reaches the set value, a HW ZQ calibration is performed and the results are automatically pushed into the PHY without the need to set the frc_msr bit.

To answer your specific questions:

1. I think this bit doesn't need to set when HW caliibration is used according to description of this bit below in refference manual. 

The frc_msr bit does not need to be used If performing the Hardware (automatic) procedures of the following:

Read DQS Gating Calibration

Read Calibration

Write Calibration

Write Leveling Calibration

That is because the automatic routine to perform the calibration is necessarily forcing the update of the PHY. But there is one exception:

Steps 33 - 35 of the Read DQS Gating Calibration has the SW read the value of the HW_DG_UP# fields and manually update the DG_HC_DEL# fields with a new value that is one less then the value found in the HW_DG_UP# fields. After these fields are updated manual (as part of the automated procedure), then the frc_msr bit must be used.

But, there are other register changes in the PHY section that do require the frc_msr bit to be set. They include:

ZQ_HW_FOR measurements

Any changes to the Write or Read delay values sent to the pads.

Any changes to the Fine tune duty cycle adjust register(s)

2.However, you mentioned it is in ddr calibration script.There is a specific order that the parameters must be loaded, and it the order is not followed, then the MMDC will have problems.

Yes that is correct. Make all changes to the PHY registers together and absolutely before intializing the MMDC by programming the MMDC_MDCTL register. Best practice is to make the changes before setting any of the MMDC registers, but this is not really a requirement. There is no valid reason to be stubborn and insist on making changes to the PHY registers in the middle of setting the main MMDC registers. It only introduces the chance for errors.

3. Calibration script also described below.

// Complete calibration by forced measurement:
setmem /32 0x021b08b8 = 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr
setmem /32 0x021b48b8 = 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr

What will complete?

What function is FRC_MSR?

As I described in the overview, the function of frc_msr is to push all of the register settings made in the PHY registers into the PHY and set them. It will also force a recalculaton of the actual delay elements used as specified by the clock period fractions set in the various calibration fields settings. It also forces pad settings (ZQ adjustment, delay settings) out to the pads.

For best practice, frc_msr should be applied at the end of the section in which PHY register settings are made. It must be made at least one time to properly set the drive strengths of the pads as determined by the initial ZQ calibration. There is no way to update the pads without it. Adding time delays to the pads is optional, but the frc_msr must be used if they are being made.

Is there a customer really objecting to using the frc_msr bits? Two small lines in the DCD. It helps ensure that the PHY is properly set up before initializing the MMDC.

Cheers,

Mark

[sugiyamatoshihi]

Hi, Mark,

Thank you for clear explanation.

I understood about frc_msr function.

Customer wants to know the reason to put it and correct location. Then, I'd just like to confirm the detail of reference manual description and reason of the frc_msr location in DCD.

However, isn't it necessary to wait frc_msr returning to 0 after set it? Although not in the description in DCD and manual.

Best Regards,

Sugiyama

[TheAdmiral]

Hi Sugiyama-san,

The "frc_msr" operation is not fully completed until the field bit returns back to '0'. You are correct.

But the time it takes to complete the operation is very short (~ 100 nanosec).

And the beginning of the initialization sequence of DDR3 is very long in comparison (700 usec before any high-speed signals are transmitted on the pads). So it is not necessary to add a wait in the DCD and poll for the bit to return to '0'.

Once the MMDC has been initialized, then it may become important to monitor the frc_msr bit depending where in a SW driven routine it is being used. But that will be done by SW, and not in the DCD. So it is not a question for the DCD initialization script.

Cheers,

Mark

[sugiyamatoshihi]

Hi, Mark,

Thank you very much for your clear explanation.

I fully understood.

Thanks 

Sugiyama