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ENET_REF_CLK for I.MX6QuadPlus

Question asked by Takayuki Ishii on Oct 6, 2017
Latest reply on Nov 26, 2017 by Takayuki Ishii
Branched to a new discussion

Hello

 

My customer use i.MX6Quad Plus with PCIe and gigabit-ethernet.

In migration guide(EB810) section 13 Peripherals,

it say that 

• Added a mux to the ENET reference clock to enable clocking direct from ENET PLL. In i.MX 6Dual/6Quad, the reference clock must be sourced from ENET_TX_CLK pad.

 

But I can not find a difference in Reference Manual.

  1) Is it meen that register setting is not changed, but it not request a external connection between ENET_REF_CLK

       and GPIO_16. is it correct?

 

The other hand, 

I think that it need not only frequency stability but also duty-cycle,

because RGMII interface use both edge of reference clocks for data and control.

(Reference manual section 23.6.18.2 RGMII interface).

But it is not cleared in datasheet.

 

I show following community threads,

ENET_REF_CLK (ball V22) duty-cycle requirements on i.MX6 

i.MX6Q ENET.REF_CLK input 

 

 

  2) Which is correct requirement of frequency stability, +-50ppm or +-25ppm?

  3) How about duty-cycle requirement. 45% - 55% is correct? or 48% - 52% is requested?

 

Best regards,

Ishii.

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