AnsweredAssumed Answered

Problem with interrupt detection in Full Chip Simulation in HiWave

Question asked by Robert Swan on Oct 6, 2017
Latest reply on Oct 12, 2017 by Robert Swan

HiWave V6.1, packaged with the demo version of CodeWarrior 5.2.  Target processor is MC9S12C128.  Working in assembly language.

I have timer interrupts scheduled for output compare on T0, T6 and T7 and have set breakpoints at the start of each interrupt handler but the simulator sometimes "misses" interrupts.

What appears to be happening is that, if the simulator is already running inside one interrupt handler when the timer counter clicks over to match another compare register, the appropriate bit of TFLG1 doesn't get set, so it won't know to simulate an interrupt after RTI.

The simulator works correctly if I single-step to and through the RTI (*).  Needless to say, this gets pretty tedious.

I hope that makes sense.  Is this a known problem?  Is there a workaround?  I tried setting breakpoints at every RTI instruction, hoping that a single-step from there might sort it out, but that didn't seem to help.  I guess that the simulator needs to be single-stepping right at the moment the timer clicks over to match.

I'd welcome any suggestions.

 

(*) on reflection, it'd probably work if I just single-stepped until the bit got set in TFLG1.  Still no fun.

Outcomes