I have a setup using using 4 DMA channel for SAI RX/TX and SPI RX/TX.
SAI DMA is running in circular mode ( 10 chained tcd's) , and the for SPI DMA is handling data transaction of fixed specified length, writing data to external memory. (Single tcd)
Both DMA setups run perfectly if the running alone. And when operating in a synchronous setup where data received from SAI is written to SPI immediately after SAI DMA has finished a tcd, the system seems to operate fine.
But when SPI transaction are started asynchronous to the SAI part, i see that the ERQ bit of the channel handling SPI TX often gets cleared and the SPI DMA stalls.
I have tried using different DMA channel, but so far it is always the ERQ bit of the SPI TX channel that gets cleared.
When the DMA stalls i can break my system and set the relevant bit in the ERQ register and the system is able to continue operation for a short time before failing again. I see no errors reported in the DMA status registers.
I have set breakpoint in all parts of the code accessing the ERQ bits ( ERG/SERQ/CERG registers), but none of these are triggered when failing..
Any suggestions will be appreciated.