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64 bit DDR controller configuration using spd not bootup(UBOOT)

Question asked by dhana sekaran on Sep 22, 2017
Latest reply on Oct 12, 2017 by dhana sekaran

Hi!

      we use T4240 processor with 4 GB( DDR3L)  connected in DDRC1- Bus width 64bit ,  2GB( DDR3L) connected in DDRC2 Bus width 32bit and DDRC3 don't have any DDR Ram. We configuring DDR ram by using spd Value in Uboot. .  when DRRC1 as 64bit and DRRC2 as 32bit the U-boot hangs.But when configuration DRRC1 and DRRC2 as 32bit U-Boot works fine and mapped as 4GB. Any suggestion Please!

 

BOOTED UP fine log:

U-Boot 2016.012.0+ga9b437f (Jul 11 2017 - 11:48:39 +0530)

 

CPU0:  T4240, Version: 2.0, (0x82400020)
Core:  e6500, Version: 2.0, (0x80400120)
Clock Configuration:
       CPU0:1000 MHz, CPU1:1000 MHz, CPU2:1000 MHz, CPU3:1000 MHz,
       CPU4:1000 MHz, CPU5:1000 MHz, CPU6:1000 MHz, CPU7:1000 MHz,
       CPU8:1000 MHz, CPU9:1000 MHz, CPU10:1000 MHz, CPU11:1000 MHz,
       CCB:733.333 MHz,
       DDR:600  MHz (1200 MT/s data rate) (Asynchronous), IFC:183.333 MHz
       FMAN1: 733.333 MHz
       FMAN2: 733.333 MHz
       QMAN:  366.667 MHz
       PME:   366.667 MHz
L1:    D-cache 32 KiB enabled
       I-cache 32 KiB enabled
I2C:   ready
SPI:   ready
DRAM:  Initializing....using SPD
intractive dhana
Detected UDIMM
Detected UDIMM
total 2 GB
total 2 GB
 CONFIG_PPC
no interleaveing inside law
no interleaveing inside law
spl build 0     config ramboot 02 GiB left unmapped
4 GiB (DDR3, 32-bit, CL=9, ECC off)
VID: Could not find voltage regulator on I2C.
Warning: Adjusting core voltage failed.
Flash: ERROR: too many flash sectors
256 MiB
L2:    2 MiB enabled
enable l2 for cluster 1 fec60000
enable l2 for cluster 2 feca0000
Corenet Platform Cache: 1 MiB enabled
Using SERDES1 Protocol: 27 (0x1b)
Using SERDES2 Protocol: 27 (0x1b)
Using SERDES3 Protocol: 1 (0x1)
Using SERDES4 Protocol: 9 (0x9)
NAND:  0 MiB
MMC:   FSL_SDHC: 0
*** Warning - bad CRC, using default environment

 

PCIE Switch Initialize all portsPCIe1: Root Complex, no link, regs @ 0xfe240000
PCIe1: Bus 00 - 00
PCIe2: disabled
PCIe3: Root Complex, no link, regs @ 0xfe260000
PCIe3: Bus 01 - 01
PCIe4: Root Complex, no link, regs @ 0xfe270000
PCIe4: Bus 02 - 02
In:    serial
Out:   serial
Err:   serial
Net:   Invalid SerDes2 protocol for T4240RDB
Fman1: Uploading microcode version 108.4.5
Could not get PHY for FSL_MDIO0: addr 0
Failed to connect
Could not get PHY for FSL_MDIO0: addr 1
Failed to connect
Could not get PHY for FSL_MDIO0: addr 2
Failed to connect
Could not get PHY for FSL_MDIO0: addr 3
Failed to connect
Fman2: Uploading microcode version 108.4.5
Could not get PHY for FSL_MDIO0: addr 0
Failed to connect
Could not get PHY for FSL_MDIO0: addr 0
Failed to connect
Could not get PHY for FSL_MDIO0: addr 0
Failed to connect
Could not get PHY for FSL_MDIO0: addr 0
Failed to connect
FM1@DTSEC1 [PRIME]
Error: FM1@DTSEC1 address not set.
, FM1@DTSEC2
Error: FM1@DTSEC2 address not set.
, FM1@DTSEC3
Error: FM1@DTSEC3 address not set.
, FM1@DTSEC4
Error: FM1@DTSEC4 address not set.
, FM1@DTSEC9
Error: FM1@DTSEC9 address not set.
, FM1@DTSEC10
Error: FM1@DTSEC10 address not set.
, FM2@DTSEC1
Error: FM2@DTSEC1 address not set.
, FM2@DTSEC2
Error: FM2@DTSEC2 address not set.
, FM2@DTSEC3
Error: FM2@DTSEC3 address not set.
, FM2@DTSEC4
Error: FM2@DTSEC4 address not set.
, FM2@DTSEC9
Error: FM2@DTSEC9 address not set.
, FM2@DTSEC10
Error: FM2@DTSEC10 address not set.

Hit any key to stop autoboot: 10

 

 

BOOT UP Fail log:

CPU0:  T4240, Version: 2.0, (0x82400020)
Core:  e6500, Version: 2.0, (0x80400120)
Clock Configuration:
       CPU0:1000 MHz, CPU1:1000 MHz, CPU2:1000 MHz, CPU3:1000 MHz,
       CPU4:1000 MHz, CPU5:1000 MHz, CPU6:1000 MHz, CPU7:1000 MHz,
       CPU8:1000 MHz, CPU9:1000 MHz, CPU10:1000 MHz, CPU11:1000 MHz,
       CCB:733.333 MHz,
       DDR:800  MHz (1600 MT/s data rate) (Asynchronous), IFC:183.333 MHz
       FMAN1: 733.333 MHz
       FMAN2: 733.333 MHz
       QMAN:  366.667 MHz
       PME:   366.667 MHz
L1:    D-cache 32 KiB enabled
       I-cache 32 KiB enabled
Reset Configuration Word (RCW):
       00000000: 1606000f 0f0f0f0f 00000000 00000000
       00000010: 6c360848 007f4c00 1c026000 15000000
       00000020: 00080000 ee0000ee 00000000 000287fc
       00000030: 00000000 50000000 00000000 00000028
I2C:   ready
Board: T4240RDB, SERDES Reference Clocks:
       SERDES1=100MHz SERDES2=156.25MHz
       SERDES3=100MHz SERDES4=100MHz
SPI:   ready
DRAM:  Initializing....using SPD
DDR Interactive
 dimm ctrl no 0
 dimm ctrl no 1
n_ranks 1
n_ranks 1
Detected UDIMM
Detected UDIMM
hwconfig has unrecognized parameter for ctlr_intlv.
hwconfig has unrecognized parameter for ctlr_intlv.
total 4 GB
total 2 GB
 CONFIG_PPC
4 GiB left unmapped
6 GiB (DDR3, 64-bit, CL=11, ECC off)

 

 

Thanks regards!

dhanasekaran K

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