How many core cycles take a 32 byte / 16 byte = 16 byte division instruction on a MKL17Z128?

[MAPC]

Hello,

Can anybody tell me how many core cycles does a 32 byte / 16 bytes = 16 byte division instruction take on a MKL17Z128?

How to optimize the compiler (both in KDS and in MCUXpresso) in order to produce the minimal set of assembly instructions for that?

I haven't found any specific information about that, not even in ARM Cortex M0 Plus Manual.

Best regards,

Marco Coelho

DFAE - Siletec Eletronica

[kerryzhou · Accepted solution]

Hi Marco,

   Actually, the core cycles take a 32 byte / 16 bytes is determined by your IDE code.

   I think you can write a small example about 32 byte / 16 bytes in the IDE you are using, then debug the code, check the according asm code.

   After you get the according asm code, please refer to my attached document: Cortex-M0+ Technical Reference Manual.pdf.

  Page 26, chapter 3.3 Instruction set summary.

   You can find each assembler cycles, then just according to table 3-1, to calculate your 32 byte / 16 bytes asm cycles.

   Take care, higher optimization will caused smaller ASM code.

  Please try it on your side.

If you still have question about it, please let me know!

Have a great day,
Kerry

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