Hello,
I'm implementing a function to store data when the Watchdog timer interrupt occur and then do a reset. However the IVOR12 interrupt never rise.
I am trying to do something like that:
On "__asm void INTC_InitINTCInterrupts( void )" function I set where the interrupt should rise.
/* set IVOR12 interrupt handler start address */
lis r5, IVOR12_Interrupt@h /* Save addr of function into r5 */
ori r5, r5,IVOR12_Interrupt@l
mtIVOR12 r5
Following there are the functions that should execute after an IVOR12 Interrupt event.
void IVR12_Int(void)
{ write_values(); /* Write data to emulated eeprom */
sbc_reset_request(); /* Do a reset */
}
#pragma push /* save the current state */
#pragma force_active on
//#pragma function_align 16 /* We use 16 bytes alignment for Exception handlers */
/** Handle the interrupt source by jumping to the ISR branch table (IACKR) */
__declspec(interrupt)
__declspec(section ".__exception_handlers")
asm void IVOR12_Interrupt(void)
{
nofralloc
prolog:
stwu r1, -0x50 (r1) /* Create stack frame */
stw r0, 0x24 (r1) /* Store r0 working register */
mfspr r3, 571
e_stw r3, 16(r1) // and save CSRR1
mfspr r3, 572
mtspr 572, r3
stw r0, 0x28 (r1) /* Store r3 */
lis r0, IVR12_Int@h /* Read pointer into ISR Vector Table & store in r3 */
ori r0, r0, IVR12_Int@l
/* Save rest of context required by EABI */
stw r12, 0x4C (r1) /* Store r12 */
stw r11, 0x48 (r1) /* Store r11 */
stw r10, 0x44 (r1) /* Store r10 */
stw r9, 0x40 (r1) /* Store r9 */
stw r8, 0x3C (r1) /* Store r8 */
stw r7, 0x38 (r1) /* Store r7 */
stw r6, 0x34 (r1) /* Store r6 */
stw r5, 0x30 (r1) /* Store r5 */
stw r4, 0x2C (r1) /* Store r4 */
mfcr r3 /* Store CR */
stw r3, 0x20 (r1)
mfxer r3 /* Store XER */
stw r3, 0x1C (r1)
mfctr r3 /* Store CTR */
stw r3, 0x18 (r1)
mflr r3 /* Store LR */
stw r3, 0x14 (r1)
/* Branch to ISR handler address from SW vector table */
mtlr r0 /* Go to IVR12_Int function */
mfspr r3,570 // Get CSRR0 and pass it to the C function
lhz r4,0(r3) // pass also the current instruction to the C function
blrl /* Branch to ISR, but return here */
epilog:
//stw r3, 0x28 (r1) /* Store r3 */
//lis r3, sbc_reset_request@h /* Read pointer into ISR Vector Table & store in r3 */
//ori r3, r3, sbc_reset_request@l
/* Branch to ISR handler address from SW vector table */
//mtlr r3 /* Store ISR address to LR to use for branching later */
//blrl /* Branch to ISR, but return here */
/* Restore context required by EABI (except working registers) */
lwz r3, 0x14 (r1) /* Restore LR */
mtlr r3
lwz r3, 0x18 (r1) /* Restore CTR */
mtctr r3
lwz r3, 0x1C (r1) /* Restore XER */
mtxer r3
lwz r3, 0x20 (r1) /* Restore CR */
mtcrf 0xff, r3
lwz r5, 0x30 (r1) /* Restore r5 */
lwz r6, 0x34 (r1) /* Restore r6 */
lwz r7, 0x38 (r1) /* Restore r7 */
lwz r8, 0x3C (r1) /* Restore r8 */
lwz r9, 0x40 (r1) /* Restore r9 */
lwz r10, 0x44 (r1) /* Restore r10 */
lwz r11, 0x48 (r1) /* Restore r11 */
lwz r12, 0x4C (r1) /* Restore r12 */
/* Disable processor recognition of interrupts */
wrteei 0
/* Ensure interrupt flag has finished clearing */
mbar 0
/* Restore Other Working Registers */
lwz r3, 0x24 (r1) /* Restore r0 */
mtspr 571, r3
lwz r3, 36(r1)
addi r1, r1, 80
rfmci
}
#pragma force_active off
#pragma pop
Thanks,
Josep Gorgues
