The datasheet for the MKV5X has the following values in Table 17 for the PLL:
Reference Frequency Range: 8 to 16 MHz
Ipll @ 176 MHz: 2.8 mA (Note says fpll_ref = 8 MHz, VDIV = 22, 8 * 22 = 176 MHz)
Ipll @ 360 MHz: 4.7 mA (Note says fpll_ref = 8 MHz, VDIV = 45, 8 * 45 = 360 MHz)
This seems to indicate that the feedback for the PLL comes directly from the VCO output.
However, this contradicts Figure 32-1 in the reference manual. This figure shows the feedback being derived from the fixed divide-by-2 MCGPLLCLK output. I confirmed using the FlexBus clock output pin and the PIT that the PLL N-divider appears to actually be connected to MCGPLLCLK2X. Can you please confirm if the following markup is correct?