Dear all,
i have actually a MCU connected to imx6q, in the classic MISO->MISO, MOSI->MOSI. Actually Linux is master and MCU is salve. All works fine. I would try, and as far as i know, with same wiring it should be possible, an inversion of role. Linux slave and MCU master. About MCU side thing is simple. About linux seems slave mode is not supported. Is this possible ? I found also a possible patch:
[v2,8/8] spi: imx: Add support for SPI Slave mode for imx53 and imx6 chips - Patchwork
Any help to have imx6q as SPI configured as slave is appreciated.
Regards,
angelo
Hi Angelo,
mx6 slave driver support has been accepted recently:
Can you try linux-next tree, that has this support in place?
Regards,
Fabio Estevam
The link is failure,could you attach a new link please?
thx!
Hi Igor,
thanks for the support.
I implemented a minimal spi-slave linux driver, it works fine. But there is something that is not clear from the errata and that maybe you can clarify.
I have IMX6QP6AVT1AA-SBAQ1636 (for mask reference).
1) In the errata, and RM datasheet as well, it is said that for slave mode, SS_CTL bit must be set to 0 (no input chip select considered) and to always set BURST_LENGTH.
By the way, if from master side i fully disable CS and just set BURST_LENGTH on imx6q rx side, i can't get any rx interrupt happening. CS must anyway be generated at least as start of transfer, seems.
2) So, from1, if i keep master side toggling CS, it selects and de-select CS for each byte. In this new scenario i cannot in any way use BURST_LENGTH to have an interrupt for multiple bytes, seems the limit is the CS deselecting (going up) so max 1 byte actually.
These 2 points above are someway confusing me, i thought i could read i.e. a burst of 160 bit (20 bytes) without any care on CS. But seems not.
Every clarification is welcome.
Thanks,
Angelo
Hi angelo
one can consider ecspi errata
https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
and try patches on
http://lists.infradead.org/pipermail/linux-arm-kernel/2017-April/501262.html
Best regards
igor
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