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Exception IVOR6 and IVOR33

Question asked by Baiming Shao on Sep 15, 2017
Latest reply on Sep 18, 2017 by David Tosenovjan



I have a question regarding exception IVOR6 and IVOR33 for MPC5777c. When I have a divide by 0 exception, I am expecting IVOR33, however, IVOR6 was triggered. And ESR[PIL] and ESR[VLEMI] are set. However, if I disable SPEFSCR[FDBZE], no exception is detected. So, the exception must somehow still related to divide by 0, it just IVOR33 are not triggered.


Any idea?