Marco Fratini

LPC4088 and external SDRAM issues

Discussion created by Marco Fratini on Sep 13, 2017
Latest reply on Sep 15, 2017 by Marco Fratini

Good morning. I've been working on a custom board based on LPC4088 and external SDRAM chip IS42S16400J, under IAR EWARM 6.70. 


The CPU is set to run at 108Mhz and the EMC a 54Mhz.


I'm using the init routines from the LPCOPEN bundle v2.10 (I think it's the latest one). 

The chip is mapped to block 0 (address 0xA0000000).


I customized the init structure for my memory chip as follows: 


STATIC const IP_EMC_DYN_CONFIG_T IS42S16400J_6BL_config = {
     EMC_NANOSECOND(64000000 / 4096),
     0x01,                    /* Command Delayed */
     EMC_NANOSECOND(15),     /* tRP */
     EMC_NANOSECOND(42),     /* tRAS */
     EMC_NANOSECOND(66),     /* tSREX */
     EMC_NANOSECOND(15), /* tAPR */     //Using trp
     EMC_CLOCK(3),          /* tDAL */
     EMC_CLOCK(2),          /* tWR */
     EMC_NANOSECOND(60),     /* tRC */
     EMC_NANOSECOND(66),     /* tRFC */
     EMC_NANOSECOND(66),     /* tXSR */
     EMC_NANOSECOND(12),     /* tRRD */
     EMC_CLOCK(0x02),     /* tMRD */
               EMC_ADDRESS_DYCS0,     /* EA Board uses DYCS0 for SDRAM */
               2,     /* RAS */

               EMC_DYN_MODE_CAS_2 |

               EMC_DYN_CONFIG_DATA_BUS_16 |
               /*EMC_DYN_CONFIG_LPSDRAM |*/
               EMC_DYN_CONFIG_4Mx16_4BANKS_12ROWS_8COLS |
          {0, 0, 0, 0},
          {0, 0, 0, 0},
          {0, 0, 0, 0}


I just added a missing RBC check that I got from LPC43XX sourc code. It's the following:

/* is it high performance RBC mode? */
          if (!(Dynamic_Config->DevConfig[ChipSelect].DynConfig & EMC_DYN_CONFIG_LPSDRAM)) {
               /* yes, it is */
               /* getting the number of banks  */
               if (!(Dynamic_Config->DevConfig[ChipSelect].DynConfig & (0x7 << EMC_DYN_CONFIG_DEV_SIZE_BIT))) {
                    /* 2 banks => 1 bank select bit */
                    Col_len += 1;
               else {
                    /* 4 banks => 2 bank select bits */
                    Col_len += 2;


Well, I think I said everything, but just ask if you need more details. So I can describe "the symptoms". 


After initialization of EMC controller and SDRAM chip, my app executes some SDRAM tests that are ALWAYS passed with success. These tests are taken from the LPCOPEN projects mentioned above (mem_tests.c, which contains the walking tests and pattern tests). It also passes succesfully some other tests we had already used in the past. 

I'm still in debugging phase of the project, so my code continuously runs some debug checks such as writing some placehoders bytes in my structured variable placed in the external RAM and reads them back. After less than a minute one of this byte is written badly: 0xAF instead of  0xAA. It's deterministic. On the other hand this symptom is raised immediately as soon as I put this structured variable in the "Live Watch" window in IAR. Surely the debugger triggers accesses to the external RAM to show me that variable. This structured variable is about 17Kbytes.

Also, while debugging, I get bad writings at the same positions and with the same bad values. 


My attempts to solve the problems were:

- Lower the frequencies of CPU to 60Mhz and EMC to 30Mhz;

- "Playing" a little with the timings of the chip;

- Trying different settings such as RBC and BRC, busrt types...;


In most cases I had no changes and sometimes the tests failed.


Thanks for your time.