referring to reset circuit in the schematic of your reference design from Embedded Planet, DES0541_11; page 2:
PMIC_POR_B is connected to R60, but R60 is NOPOP so it will not enter MR_b input of the reset circuit U9.
Instead, PMIC_POR is bypassing the reset circuit through R63 into AND-gate U12 and anded with the RST_ output from U9.
Is there any particular reason why PMIC_POR is bypassing the reset circuit U9?
Could PMIC_POR be connected to MR_b through R60 and instead R63 be NOPOP?
regards Trond Inge