Fabio Pereira

INC and DEC timings in direct addressing mode

Discussion created by Fabio Pereira on Sep 16, 2008
Latest reply on Sep 17, 2008 by Fabio Pereira

Maybe this is a silly question but while researching on code optimization, I realized that the timings for the INC and DEC instructions when using the direct addressing mode are somewhat strange when compared to other addressing modes and instructions.

According to the HCS08 Reference Manual and several (all) device data sheets, the INC opr8a instruction executes in 5 BUSCLK cycles.

When looking on other instructions using DIR addressing mode we find slightly lower timings: ADC, ADD, AND, BIT, CMP, EOR, ORA, etc. All these instructions execute in 3 BUSCLK cycles when using DIR addressing mode.

Nevertheless, INC and DEC (and shifts too), when using DIR mode execute in 5 BUSCLK cycles.

In fact, it is possible to exchange the INC opr8a instruction with a two-instruction sequence such as:

LDA #1       ; 2 cycles
ADD opr8a  ; 3 cycles

Which runs in the same time!

My question is: why a two-instruction sequence runs in the same time as a single instruction, which is supposed to be faster?

Looking into the supposed micro-operations sequence, it is difficult to understand why INC oper8a needs 2 more cycles than ADD oper8a, as they use the hardware (ALU) in almost the same way.

Of course I am not neglecting the fact that INC needs to load one input of the ALU with 1 and the other one with the operand read from the memory, but that could be surely done in parallel with the operand fetch.

Anyone else felling there is some room for improvement? Maybe we could get a deeper explanation on why it is not possible to run INC oper8a in 3 BUSCLK cycles.

Maybe I (probably!) missed something ...

Best regards,