For Exp: Can K30 handle about 200kHz(other hand every 5us) PIT interrupt?
K30 PIT clock source is the BUS clock which can be set to the max value 50M. And there is no restriction for PITx_LDVALn. So it can generate interrupt in a very high frequency.
The only problem of high interrupt frequency is whether the MCU has enough time to deal with so much interrupt. If not, interrupt will be pending and then lost.
So thus assuming a 100MHz core-clock, 5us encompasses 500 instruction cycles. ASSUMING a 'couple dozen' clocks are consumed by interrupt hardware processes, that still leaves a 'fair number' of clocks for a 'lean' interrupt handler and 'leftovers' for the rest of the work to be done... 200KHz is certainly 'not unreasonable' to handle.
Thanks for reply
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