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Multiple HSYNC in MIPI DSI Frame using i.Mx 6 DL

Question asked by Olivier CHIRON on Sep 8, 2017
Latest reply on Sep 11, 2017 by igorpadykov

Hi,

 

I try to integrate a MIPI DSI module for QVGA screen ( 320 x 240 ) on i.Mx 6 dual Lite.

 

In some configurations, we observe undesirables HSYNC packets in the MIPI DSI Frame ( the

 

MIPI DSI is configured as follow : MIPI CLOCK 80 MHz, 2 LANE Active, Low power mode transparent.

The frame buffer configuration is given hereafter

 

For instance, in this frame buffer configuration, we have no problem. We observe, one HSYNC in the MIPI-DSI frame for each line.

static struct fb_video_mode truly_lcd_modedb[] = {

{

                « QVGA », 58, 320, 240, 163000,   // name, refresh, xres, yres, pclk (ps)

                68, 20,   // HBP, HFP

                18, 4,   // VBP, VFP

                16, 4,   // HSYNC period, VSYNC perdod

                FB_SYNC_OE_LOW_ACT,

                FB_VMODE_NONINTERLACED,

                0,

                },

} ;

 

But in this configuration ( same configuration with pclk period modified ), with observe one undesired HSYNC following the 24 bits packed pixel stream.

static struct fb_video_mode truly_lcd_modedb[] = {

{

                « QVGA », 58, 320, 240, 162000,   // name, refresh, xres, yres, pclk (ps)

                68, 20,   // HBP, HFP

                18, 4,   // VBP, VFP

                16, 4,   // HSYNC period, VSYNC perdod

                FB_SYNC_OE_LOW_ACT,

                FB_VMODE_NONINTERLACED,

                0,

                },

} ;

 

In the bad configuration, with observe the MIPI_D0N and MIPI_D1N s using oscilloscope ( with integrated MIPI DSI decoder module )

Bad configuration Multiple HSYNC in MIPI Frame

 

Can you see a problem in our configuration ? Our linux Kernel version is 3.0.35.

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