iMX7 Solo, halt CPU by JTAG

[cyuk]

I am trying to connect my own board containing an iMX7 Solo to a j-link debugger. The debugger and j-link commander software works with the sabre dev. board (which contains a DUAL core). Can there be a difference between the solo and dual core versions? Has anyone successfully connected to the WaRP7 dev. board with an j-link and j-link commander?

In j-link commander, I have been told to specify the device to be a Cortex-A7 as no script should be necessary. The output is attached below.

I believe the JTAG communication works, because the core is found to be Cortex-A7 r0p5 (how should it know it without communication?). Furthermore, in IAR embedded workbench suite, I can single step a demo program and read/write registers.

J-link commander terminal:

SEGGER J-Link Commander V6.14c (Compiled Mar 31 2017 17:46:20)
DLL version V6.14c, compiled Mar 31 2017 17:45:52

Connecting to J-Link via USB...O.K.
Firmware: J-Link V9 compiled Jul 24 2017 17:37:57
Hardware version: V9.40
S/N: XXXX
License(s): FlashBP, GDB
OEM: SEGGER-EDU
VTref = 1.790V

Type "connect" to establish a target connection, '?' for help
J-Link>connect
Please specify device / core. <Default>: CORTEX-A7
Type '?' for selection dialog
Device>
Please specify target interface:
  J) JTAG (Default)
  S) SWD
TIF>
Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect
JTAGConf>
Specify target interface speed [kHz]. <Default>: 4000 kHz
Speed>
Device "CORTEX-A7" selected.

TotalIRLen = 4, IRPrint = 0x01
ARM AP[0]: 0x64770001, AHB-AP
ARM AP[1]: 0x44770002, APB-AP
ROMTbl 0 [0]: 00040003, CID: B105100D, PID:00-00080000 ROM Table
ROMTbl 1 [0]: 00001003, CID: B105900D, PID:04-002BB908 CSTF
ROMTbl 1 [1]: 00020003, CID: B105100D, PID:04-000BB4A7 ROM Table
ROMTbl 2 [0]: 00010003, CID: B105900D, PID:04-005BBC07 Cortex-A7
Found Cortex-A7 r0p5
6 code breakpoints, 4 data breakpoints
Debug architecture ARMv7.1
TotalIRLen = 4, IRPrint = 0x01

****** Error: Cortex-A/R (connect): Failed to temporarily halting CPU for reading CP15 registers.
TotalIRLen = 4, IRPrint = 0x01
TotalIRLen = 4, IRPrint = 0x01
Cannot connect to target.

[sinanakman]

Hi Ulrik

I don't know much about j-link as I have been primarily using another debugger (BDI3000) but 

looking at your log, it potentially tells me that soon after your board booted but before the debugger

could halt it, it perhaps crashed :

Found Cortex-A7 r0p5
6 code breakpoints, 4 data breakpoints
Debug architecture ARMv7.1
TotalIRLen = 4, IRPrint = 0x01

****** Error: Cortex-A/R (connect): Failed to temporarily halting CPU for reading CP15 registers.

  You mention that this is with your "own board containing an iMX7 Solo". Can you confirm that you are seeing the same output with the WaRP board as well. Also can you verify that your board that you are trying to connect does boot fine without the debugger connected. 

Hope this helps

Regards

Sinan Akman

[cyuk]

Hi Sinan, thanks for taking the time,

Unfortunally I don't have the WaRP board. But it seems to be the only way to get going.

As I understand it, NXP do not supply hardware nor suggest a third party solution to program their iMX processors. Bad support!

[igorpadykov]

Hi ulrik

one can check if signal JTAG_MOD=0, it is routed on connector but not
grounded as on Sabre board. Also this may be posted on segger forum as
"Cannot connect to target" error may be due to wrong J-Link i.MX7 script on some releases:
http://forum.segger.com/index.php?page=Thread&threadID=3914

Best regards
igor
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[cyuk]

Hi,

JTAG_MOD is grounded and I have also tried to pull it high once. That changed the JTAG chain as expected.

I don't see how the link you sent is related to my problem. I am not using any script for the solo CPU.

Another difference is that I have 1.8 V at the JTAG instead of 3.3 V as on the Sabre. Can that give timing issues?

Any other suggestions?

[cyuk]

Any updates?

[igorpadykov]

probably correct number of cores should be configured in script,

since script was developed by segger seems more appropriate

to post issue on segger forum.

Best regards
igor

[cyuk]

Hi,

I did. They said, that the solo core CPU has no jtag chain, and therefore a script is not needed. Just use the generic A7 core option. Is that also your opinion?

So what support do you give to customers, how buy the WaRP7 board? What debugger do you suggest them to use?

[VladanJovanovic]

Hi Ulrik,

i.MX 7 scan chain is shown in Figure 4-24. This has to be configured properly in JTAG tool, so it's really a question of Segger J-Link setup.

When you start the i.MX 7, try to boot it in serial download mode. U-boot/Linux may disable clock to jtag and thus prevent it from operating properly.

br,

Vladan