Working on optimizing transfer rates to s SPI flash I have observed quite large inter byte/word delay on the SPI bus.
My system is running 120 MHz system clock and 30 MHz SPI clock, and i am using the standard fsl_dspi_edma driver.
When transmitting multiples bytes via DMA, i see that the transfer of the each 8 data bits take about 266ns as expected, but between bytes i see a delay of ~100 ns. Transfer is done with kDSPI_MasterPcsContinuous set.
I was initially using SPI1, and as i was suspecting the delay being related to the missing FIFO on this channel i moved to SPI0 that has 4 level FIFO. However i see the same timing the channel.
Are there any ways to control interword timing on SPI transfers or is the interbyte delay expected behaviour?