I have a question about BYPASS bit and POWERDOWN bit of the Analog ARM PLL control register.
Reset value of BYPASS bit and POWERDOWN bit is "1".
I understand these Bits as follows.
Would you tell me whether my understanding is right?
- These Bits are set(cleared) by software.
- In Boot immediately after POR, Analog ARM PLL is baypassed.
- ARM core runs at low speed until these bits are set by Bootloader.
On the other hand,
The frequency of the ARM core in Boot is set by BT_FREQ(BOOT_CFG3).
"0 - ARM - 792 MHz, DDR - 396 MHz, AXI -264 MHz"
I suspect that a reset value of the register may be wrong.
(Reset value of BYPASS bit and POWERDOWN bit is "0" ? )
May I have advice?