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IMX6UL_14x14 BDSL DRAM_SDCLK0_P signal

Question asked by James Kirkman on Sep 1, 2017
Latest reply on Sep 5, 2017 by Yuri Muhin

In The IMX6UL_14x14 BDSL file the DRAM_SDCLK0_P signal is set to be bidirectional. The JTAG is unable to read the correct signal back which leads me to believe that the PAD is an output only PAD. Could you confirm this please