This question pertains to software control of the CTS signal for UART3 and UART4, operating in DCE mode, in the i.MX6.
This question is related to a previous question about CTS_B signal with DTE mode for i.MX6Solo . However, in that question, DTE mode was being used, and the discussion seemed to center on DTE vs DCE, with conflicting information and lots of confusion. The original question was never answered.
Summary of configuration, using UART3 as an example...
1. The device is in DCE mode (UARTx_UFCR, DCEDTE=0). This means that the internal CTS_B signal is routed as an output to the CTS_B pin, per Section 64.2 of the i.MX6 S/DL RM.
2. The CTS signal is connected SD3_DAT3, and so IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3, is set to 1 as required.
3. In addition, IOMUXC_UART3_UART_RTS_B_SELECT_INPUT is set to 4 as required.
I am using the CTSC/CTS bits in UCR2 to control the CTS signal. Under most conditions, this works as described in Section 64.15.4 on the i.MX6 S/DL RM. In other words, when I set the CTS bit to 0, the CTS_B pin goes high, and when I set the CTS bit to 1, the CTS_B pin goes low. Of course, CTSC is always set to 0.
However, it appears that other there are other control bits that affect the CTS_B pin. Specifically:
- If the RXEN bit of UCR2 is set to 0, then the CTS_B pin goes high, regardless of the setting of the CTSC/CTS bits in UCR2.
- If the UARTEN bit of UCR1 is set to 0, then the CTS_B pin goes high, regardless of the setting of the CTSC/CTS bits in UCR2.
My question is what are all factors that control the level of CTS_B pin when in DCE mode, when CTSC bit in UCR2 is set to 0? The i.MX6 S/DL RM implies that only the CTS bit in UCR2 controls the level of the CTS_B pin, but it appears that is not true.