Dear Freescale Forum Users, I'm going to develop a new bo...

[aval]

Dear Freescale Forum Users,
I'm going to develop a new board using an MCF5329 but I still have some doubt about the SDRAM controller I I'm not able to find answers from the reference manual. Here my doubts:
1) I can see a lot of timing examples about SDR and DDR based on the value of fSD_CLK set at 99MHZ but is seems to me that we have no registers to set it and, so, it is probably fixed at the Flexbus clock at 80MHz. Is this correct?
2) If so, I've read somewhere in Micron memory datasheet that JEDEC imposes a minimum clock frequency of 83MHz, so which kind of DDR can we use?
3) This said, I planned to use 2 SDRAM devices with x16 width and optionally mount only one of them. On which bit lanes have I to place the single device? I think on D16-D31, but I'd like to have a confirmation somewhere.

Thanks in advance,
Alessandro.

[aval]

Sorry for this second part but I'm quite sure of the SDRAM x16 connection on the high half of the bus (D16-D31) and byte lane signals BS0_B for D24-D31 (high byte) and BS1_B for D16-D23 (low byte), so I'd like to add this note.
Isn't it?

I've also set a better subject to this thread.

Thanks,
Alessandro.