Hello i.MX Community,
My team is working to optimize our i.MX6 NAND bus to maximize throughput while maintaining good margins. We are using the IMX6DQRM Rev. 3 for reference and we have a few questions we could use your help to answer:
What does the dsample_time parameter in the m_NandTiming array (Table 8-11) physically map to? Does it get used by the Boot ROM for raw NAND (Single Data Rate)?
- I see this is set to a default data_sample_time of 6 in kobs_ng's dot-kobs file, but there doesn't appear to be any other reference to it in any i.MX6 documentation or our NAND part's datasheet.
- Additionally, if I modify this parameter, update the FCB table in NAND, and then dump the registers after booting from NAND, I don't see any GPMI register changes.
Can you please confirm the m_NandTiming parameters for data_setup, data_hold, and address_setup are a 1:1 mapping with the bit fields in the GPMI_TIMING0 register? For example, if I want a data_hold equal to 10 GPMICLK cycles, should I set each parameter to 10 (0xA)?
Can you please confirm the Toggle Mode parameters in the FCB table (e.g. TMSpeed, TMTiming1_BusyTimeout) are ignored when using raw NAND (Single Data Rate).
- If so, I would also assume the GPMI registers these values set are also ignored when using raw NAND.