DDR ECC checking at u-boot for LS1046ardb

[sreeragag]

I have been trying for ECC checking in DDR for LS1046ardb from u-boot to access DDR registers. When I tried for writing to DDR_MTCR, memory write did not change the register values in the DDR_MTCR.

How can we configure the DDR testing registers from u-boot?

Also I tried with DDRv tool in the CodeWarrior. But that didn't work. The connection with CWTAP is not able to establish. How to get CWTAP connection proper? I changed the frequency of JTAG to 16000. Tried for both hard coded and QSPI boot options with JTAG. 

[yipingwang]

Hello Sreerag A G,

In u-boot, you could define CONFIG_FSL_DDR_BIST to enable built-in memory test in the header file include/configs/ls1046ardb.h.

#define CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE           0xdeadbeef
#define CONFIG_FSL_DDR_BIST     /* enable built-in memory test */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
#endif

Please refer to the following section in drivers/ddr/fsl/fsl_ddr_gen4.c.

#ifdef CONFIG_FSL_DDR_BIST
#define BIST_PATTERN1   0xFFFFFFFF
#define BIST_PATTERN2   0x0
#define BIST_CR         0x80010000
#define BIST_CR_EN      0x80000000
#define BIST_CR_STAT    0x00000001
#define CTLR_INTLV_MASK 0x20000000
        /* Perform build-in test on memory. Three-way interleaving is not yet
         * supported by this code. */
        if (getenv_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) {
                puts("Running BIST test. This will take a while...");

...

                mtcr = BIST_CR;
                ddr_out32(&ddr->mtcr, mtcr);

Regarding DDRv problem, please make sure there is valid RCW on the target board, QCVS tool cannot support hard-coded RCW. If the target board is empty, please refer to the first section in Use CodeWarrior for ARMv8 to Debug U-boot and Linux Kernel and Bring up Bare Boards  to program RCW on the target board.

 Please refer to DDRv user manual https://www.nxp.com/docs/en/user-guide/QCVS_DDR_User_Guide.pdf .

 Please refer to DDR Controller Configuration on LS2085/LS2080 Bringing up 

Have a great day,
TIC

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[tracysmith]

Customers need the ability to test do ECC testing or unit tests to test for machine check errors.  Does NXP have any tests to validate the ECC by inducing a DDR error?