I have the TPM module running off the OCERSCLK from an exterior crystal at 6.144MHz. When I have the core clock set to run off the same crystal, my TPM output is perfect, exactly as I expect. When I change the Core Clock to 3MHz HIRC internal clock, the TPM output looks pretty close to normal, although it seems to be slighly affected by the clock change. When I change the Core Clock to 2MHz LIRC, the TPM output is not normal at all. Channel interrupts occur out of the blue when they shouldn't and the counters do not appear to be counting properly. When I change the Core Clock to 8MHz LIRC, there is no TPM output at all. Any idea what is causing this?
When I read through the user's manual, the best I could find is the excerpt below.
Could my core clock be causing problems with the TPM module in a similar manner to the external clock mode even though I'm not using the external clock mode? If so, how? I thought that the TPM module would be isolated from the core clock since it is running off it's own clock. Is there a rule-of-thumb for this?