Waking up after setting Sleepdeep and executing a WFI will leave UART0 unresponsive.Is there anything explicit that needs to be done to make UART0 usable again?
The following report may help:https://community.nxp.com/message/421247
There are binary files for the FRDM-K64F here which include low power modes for checking the UART wakeup response: http://www.utasker.com/kinetis/FRDM-K64F.html
Thanks for your reply. I had seen that post before, but it does not explain
something needs to be done after wake up to make the UART and Systick
work again. It says that in STOP mode the UART and Systick will stop
working, but it does not say how you make them work again after going back
to RUN mode. I don't need to use the UART or Systick as "wake up sources"
to trigger the transition from STOP mode back to RUN mode. I'm using a GPIO
pin interrupt as the wake up source and that is working. My problem is how
make the UART and Systick work again after waking up.
On Mon, Aug 28, 2017 at 4:05 PM, mjbcswitzerland <firstname.lastname@example.org>
There is nothing needed after returning from STOP mode to RUN mode - the clocks that had stopped will automatically be re-enabled and the peripherals fully functional again.
If neither UART nor Systick are operating afterwards there must be another problem involved (eg. the GPIO wake-up may be causing the wake up to take place but not be handled correctly to allow the code to continue correctly (?)).
Attached is the low power control module from the uTasker project (you will see it does nothing special on return from WFI in STOP mode) as reference - you can get a complete and fully operating K64 low power solution on GITHUB or take the required pieces from it if you prefer.
Thanks again. I finally found my problem. The key to the problem that I was
having is in the following text:
*(from the K64F RM - Chapter 25 Multipurpose Clock Generator (MCG), table
*• When entering Low Power Stop modes (LLS or VLPS) from PEE mode, on exit
MCG clock mode is forced to PBE clock mode. C1[CLKS] and S[CLKST] will be
*configured to 2’b10if entering from PEE mode or to 2’b01 if entering from
*C5[PLLSTEN0] will be force to 1'b0 and S[LOCK] bit will be cleared without
*• When entering Normal Stop mode from PEE mode and if C5[PLLSTEN]=0, on
*the MCG clock mode is forced to PBE mode, the C1[CLKS] and S[CLKST] will
configured to 2’b10 and S[LOCK] bit will clear without setting S[LOLS]. If
*C5[PLLSTEN]=1, the S[LOCK] bit will not get cleared and on exit the MCG
continue to run in PEE mode.
I'm initialzingthe MCG clock mode to be PEE at boot time. From the note
MCG clcok mode is switched to PBE when waking up from LLS stop mode. This
was causing the UART and the Systick timer to stop working. All I needed to
do in the LLWU ISR was to set the MCG clock mode back to PEE.
On Tue, Aug 29, 2017 at 3:06 AM, mjbcswitzerland <email@example.com>
Yes, the exit from LLS or VLPS requires the PLL to be reconfigured (if being used).
However, your thread suggests that you were exiting from STOP mode (sleepdeep + wfi) which is why I wrote that there is nothing else needed.
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