I was looking to add some addressable registers to the CPLD on my C290PCIe-RDB Rev C board. I have already used the Altera Programming Tool to verify the contents of the CPLD on the board against the oamp-v2.2.pof design file.
But to build my own image, I would need the pinout and timing constraints .sdc file that is not provided in the C29X_PCIE_DESIGN_FILES.zip download. Otherwise, I would stand a good chance of screwing up the timing of the IFC address decode that occurs within the CPLD.
Is the .sdc for the C29X PCIE CPLD available?