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C290PCIe-RDB Rev C board timing constraints .sdc file request

Question asked by mikedubya on Aug 14, 2017
Latest reply on Sep 5, 2017 by mikedubya
Branched from an earlier discussion

I was looking to add some addressable registers to the CPLD on my C290PCIe-RDB Rev C board.  I have already used the Altera Programming Tool to verify the contents of the CPLD on the board against the oamp-v2.2.pof design file.


But to build my own image, I would need the pinout and timing constraints .sdc file that is not provided in the download.  Otherwise, I would stand a good chance of screwing up the timing of the IFC address decode that occurs within the CPLD.


Is the .sdc for the C29X PCIE CPLD available?