We are still in development phase with a P1020 QorIQ processor. We plan on implemenenting a 4-lane PCIe solution, where the whole design consists of a single PCB with RC and EP on the same board, the PCIe link is just chip-to-chip.
As the implementation is just chip-to-chip, i became curious of the compliance measurements and how they should be interpreted. The plan for now is to do RX compliance measurements on both RX sides of the link and also to check the clock, so it's a reduced check.
However, as I understand it, the RX measurements require that the compliance test pattern (see section 4.2.8 of the PCI Express Base Specification, Rev 1.1) to be sent during the measurements.
My questions is:
How do I do the RX measurements on the P1020? Do i keep the TX in state polling.compliance (ie my other chip). Or do i use register GUTS_SRDSCR3 in the P1020 and set bits [19:23] to make sure that the RX doesn't detect an electrical idle exit?
From the P1020 reference manual, register GUTS_SRDSCR3:
Recommended setting per protocol:
PCI Express: 10011
In other words:
Receiver electrical idle detection control for Lane 0
100 Default PCI Express levels (low = 65 mV, high = 175mV)
PCI Express receiver electrical idle detection control for Lane 0.
How do i set up this register to stop the RX from exiting electrical idle?
Or is there another way?