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i.MX7D DDR Calibration

Question asked by Dieter Steininger on Aug 25, 2017
Latest reply on Aug 25, 2017 by Jan Spurek

I`m using i.MX7D with DDR3 ram on a custom board. Is DDR Calibration necessary for i.MX7D?

When running DDR Calibration (ddr_stress_tester_v2.70), i got following result:

 

============================================
        DDR Stress Test (2.6.0)
        Build: Aug  1 2017, 17:34:14
        NXP Semiconductors.
============================================

============================================
        Chip ID
CHIP ID = i.MX7 Dual (0x72)
Internal Revision = TO1.2
============================================

============================================
        Boot Configuration
SRC_SBMR1(0x30390058) = 0x00004000
SRC_SBMR2(0x30390070) = 0x29000011
============================================

============================================
        DDR configuration
DDR type is DDR3
Data width: 32, bank num: 8
Row size: 15, col size: 10
One chip select is used
Density per chip select: 1024MB
Total density is 1024MB
============================================

DDR Freq: 528 MHz

Calibration for 32-bit data bus

 

Starting Read calibration...

 

Read Delay value:  Result:
0x9e9e9e9e         0x1111
0x9c9c9c9c         0x1111
0x9a9a9a9a         0x1111
0x98989898         0x1111
0x96969696         0x1111
0x94949494         0x1111
0x92929292         0x1111
0x90909090         0x1111
0x8e8e8e8e         0x1111
0x8c8c8c8c         0x1111
0x8a8a8a8a         0x1111
0x88888888         0x0110
0x86868686         0x0000
0x84848484         0x0000
0x82828282         0x0000
0x80808080         0x0000
0x02020202         0x0000
0x04040404         0x0000
0x06060606         0x0000
0x08080808         0x0000
0x0a0a0a0a         0x0000
0x0c0c0c0c         0x0000
0x0e0e0e0e         0x0000
0x10101010         0x0000
0x12121212         0x0000
0x14141414         0x0000
0x16161616         0x0000
0x18181818         0x0000
0x1a1a1a1a         0x0000
0x1c1c1c1c         0x0000
0x1e1e1e1e         0x0000
0x20202020         0x0100
0x22222222         0x1111
0x24242424         0x1111
0x26262626         0x1111
0x28282828         0x1111
0x2a2a2a2a         0x1111
0x2c2c2c2c         0x1111
0x2e2e2e2e         0x1111

 

Final read delay = 0x0C0C0C0C
-Note: final delay is based on the center of all passing byte lanes

 

Starting Write calibration...

 

Write Delay value:  Result:
0x9e9e9e9e         0x1111
0x9c9c9c9c         0x1111
0x9a9a9a9a         0x1111
0x98989898         0x1111
0x96969696         0x1111
0x94949494         0x1111
0x92929292         0x1111
0x90909090         0x1111
0x8e8e8e8e         0x1111
0x8c8c8c8c         0x0000
0x8a8a8a8a         0x0000
0x88888888         0x0000
0x86868686         0x0000
0x84848484         0x0000
0x82828282         0x0000
0x80808080         0x0000
0x02020202         0x0000
0x04040404         0x0000
0x06060606         0x0000
0x08080808         0x0000
0x0a0a0a0a         0x0000
0x0c0c0c0c         0x0000
0x0e0e0e0e         0x0000
0x10101010         0x0000
0x12121212         0x0000
0x14141414         0x0000
0x16161616         0x0000
0x18181818         0x0000
0x1a1a1a1a         0x1110
0x1c1c1c1c         0x1111
0x1e1e1e1e         0x1111
0x20202020         0x1111
0x22222222         0x1111
0x24242424         0x1111
0x26262626         0x1111
0x28282828         0x1111
0x2a2a2a2a         0x1111
0x2c2c2c2c         0x1111
0x2e2e2e2e         0x1111

 

Final write delay = 0x06060606
-Note: final delay is based on the center of all passing byte lanes

 

Success: DDR calibration completed!!!

I dont´t know, how this result will help confguring DDR in uboot?

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