By our system, we do not use following PLLs.
- PLL3_PFD0 / PFD1 / PFD2 / PFD3- PLL4- PLL5
Do we have to set a register related to these?Can we remain a default(reset value) for registers related to these PLLs?
one can refer to the Reference Manual : chapter 184.108.40.206 Disabling / Enabling PLLs,
Dear Joan Xie-san,
Thank you for an answer.
I understood it as follows.
For PLL3_PFD0 / PFD1 / PFD2 / PFD3 - PFDx_CLKGATE bit is set to 1. (Clock gate) - PFDx_FRAC firld is left the Apter Reset value.
For PLL4 and PLL5 - Unsued PLLs are not Enabled. - Registers of PLLs are left the After Reset value.
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