Dear all,
By our system, we do not use following PLLs.
- PLL3_PFD0 / PFD1 / PFD2 / PFD3
- PLL4
- PLL5
Do we have to set a register related to these?
Can we remain a default(reset value) for registers related to these PLLs?
Best Regards,
Yuuki
one can refer to the Reference Manual : chapter 18.5.1.6 Disabling / Enabling PLLs,
Dear Joan Xie-san,
Thank you for an answer.
I understood it as follows.
For PLL3_PFD0 / PFD1 / PFD2 / PFD3
- PFDx_CLKGATE bit is set to 1. (Clock gate)
- PFDx_FRAC firld is left the Apter Reset value.
For PLL4 and PLL5
- Unsued PLLs are not Enabled.
- Registers of PLLs are left the After Reset value.
Best Regards,
Yuuki