We use SIU_SRCR[SSR] to reset the processor: this works OK on 2N45H however does not appear to work on 3N45H.
The reference manual and errata don't mention anything, but I have two PCBs where the only hardware difference is the CPU mask and the PCB with the 3N45H does not reset correctly.
As an experiment I dragged out the debugger and tried to single step over the write to SSR:
On 2N45H the next instruction after the write to SSR is 0xfffffffc and execution continues as expected.
On 3N45H the P&E debugger reportes errors