I have some questions about registers of PLL.
According to Reference Manual, the following is explained about Audio PLL.
PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM)
IMX6SDLRM Rev. 2, 04/2015 :
- 22.214.171.124.4 Audio / Video PLL (P.800)
According to "Figure 18-2. Clock Tree - Part 1"(P.784) in Reference Manaul,
the PLL4(Audio PLL) is default 630MHz.
However, the initial(reset) value of these registers are the following.
- CCM_ANALOG_PLL_AUDIO[DIV_SELECT] = 0001100（12d）
- CCM_ANALOG_PLL_AUDIO_NUM = 05F5C100h
- CCM_ANALOG_PLL_AUDIO_DENOM = 2964619Ch
In this case it does not become 630MHz.
Furthermore, the following is explained in CCM_ANALOG_PLL_AUDIO[DIV_SELECT] field description, but violates this.
"Valid range for DIV_SELECT divider value: 27~54."
Is the Reset value of the CCM_ANALOG_PLL_AUDIO_xxx register right?
CCM_ANALOG_PLL_AUDIO[BYPASS] is set to "1" by default.
Is this right?
I think that BYPASS=0(not bypass) is right.
May I have advice?