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about CCM_ANALOG_PLL_AUDIO_xxx registers of i.MX6DL

Question asked by yuuki on Aug 21, 2017
Latest reply on Aug 28, 2017 by Artur Petukhov

Dear all,

 

I have some questions about registers of PLL.

 

According to Reference Manual, the following is explained about Audio PLL.

 PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM)

 

<Reference Manual>
IMX6SDLRM Rev. 2, 04/2015 :
 - 18.5.1.3.4 Audio / Video PLL (P.800)

 

According to "Figure 18-2. Clock Tree - Part 1"(P.784) in Reference Manaul,
the PLL4(Audio PLL) is default 630MHz.


However, the initial(reset) value of these registers are the following.

 - CCM_ANALOG_PLL_AUDIO[DIV_SELECT]  = 0001100(12d)
 - CCM_ANALOG_PLL_AUDIO_NUM   = 05F5C100h
 - CCM_ANALOG_PLL_AUDIO_DENOM   = 2964619Ch

 

In this case it does not become 630MHz.

Furthermore, the following is explained in CCM_ANALOG_PLL_AUDIO[DIV_SELECT] field description, but violates this.

 "Valid range for DIV_SELECT divider value: 27~54."

 

<Question1>
Is the Reset value of the CCM_ANALOG_PLL_AUDIO_xxx register right?

 

<Question2>
CCM_ANALOG_PLL_AUDIO[BYPASS] is set to "1" by default.
Is this right?

I think that BYPASS=0(not bypass) is right.

 

May I have advice?

 

Best Regards,
Yuuki

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