AnsweredAssumed Answered

i.MX6ULL SDIO interface power up sequence & GPIO sink current

Question asked by Abin Puthiyath on Aug 21, 2017
Latest reply on Aug 22, 2017 by igorpadykov



We have a couple of questions regarding i.MX6ULL processor we are using in our latest design. Hope you can help us with it.


  1. Can the GPIO pin sink a current of 4mA without damaging the pin? 
  2. What is the current sinking capability of i.MX6ULL GPIO pins?
  3. Regarding the power up, the datasheet says the power up sequence to be in the order of:
    1. SNVS
    2. VDD_HIGH
    3. VDD_CORE

But there is no mention about when we can power the interface voltages, say, NVCC_ENET, NVCC_SD1 etc.. we have a different voltage for NVCC_SD1 (1.8V for NVCC_SD1, rest share VDD_HIGH). Where is the interface voltage placed in the power up sequence? Does it mean that we can power them up at any time before the POR is asserted?


4. We now have the VDD_SOC and DDR3L voltages at 1.35V. A single switching regulator (Max current -800mA; Regulator rated for 1A) power both the rails. Are there any problems on sharing the same rail for VDD_SOC & DDR3L?


Thanks & regards