In my target custom board , a SPI device is interfaced with IMX6 solo over the SPI bus. Now as per my understanding ,
SPI controller over the IMX6 as a master is the clock generator on the SPI bus . So it will source the clock during the \
read and write cycles over the SPI bus. So SPI controller will only poll the data from the SPI slave . SPI slave cannot
gives the interrupt to the SPI controller to read the data. But as I see in the reference manual of IMX6 solo , chapter 3 "Interrupts and DMA" table 3-1 , interrupts number 63 is dedicated for eCSPI1 . How this interrupt will work ?
Please help me to understand.