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problem of imx6q EIM

Question asked by zhen qiu on Aug 18, 2017
Latest reply on Aug 21, 2017 by igorpadykov

I'm using  imx6Q  EIM interface, when I write or read to the EIM address( ioremap for 0x08000000 already), no signal on all EIM pins, what is the problem?

the init code for EIM is:

 

static int eimdev_open(struct inode *inode, struct file *file)
{
int i;
REG_BASE = ioremap((long)0,0x02dfffff);

EIM_BASE = ioremap((long)0x08000000,2048);

CCM_CCGR2 |= 3<<14; /*enable iomux_ipt_clk_io clock*/
CCM_CCGR6 |= 3<<10; /*enable eim clock*/

for(i=0;i<16;i++){
IOMUXC_SW_MUX_CTL_PAD_EIM_AD(i) = 0; /*set EIM AD pins to EIM function*/
}

IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16 = 0; /*set EIM pins to EIM function*/
IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17 = 0;
IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18 = 0;
IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19 = 0;
IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_B = 0;
IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_B = 0;
IOMUXC_SW_MUX_CTL_PAD_EIM_OE_B = 0;
IOMUXC_SW_MUX_CTL_PAD_EIM_RW = 0;
IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_B = 0;

IOMUXC_GPR(1) &= ~ADDRS0_BITS;
IOMUXC_GPR(1) |= 2<<1; /*ADDRS3 = 10, CS0 128MB*/

IOMUXC_GPR(1) |= ACTCS0_BIT; /*ENABLE CS0*/
IOMUXC_GPR(1) &= ~ACTCS1_BIT; /*DISABLE CS1*/
IOMUXC_GPR(1) &= ~ACTCS2_BIT; /*DISABLE CS2*/
IOMUXC_GPR(1) &= ~ACTCS3_BIT; /*DISABLE CS3*/
/**********************************************************************************************/
EIM_CS0GCR1 |= MUM_BIT; /*MUM = 1,Multiplexed Mode enable*/
EIM_CS0GCR1 &= ~SRD_BIT; /*SRD = 0,READ in Asynchronous mode*/

EIM_CS0GCR1 &= ~SWR_BIT; /*SWR = 0,WRITE in Asynchronous mode*/

EIM_CS0GCR1 &= ~CSEN_BIT; /*CSEN = 0,ENABLE CS FUNCTION*/

EIM_CS0GCR1 &= ~DSZ_BITS;
EIM_CS0GCR1 |= 3<<16; /*DSZ=011, set 32bits data mod*/
EIM_CS0GCR1 |= AUS_BIT; /*AUS = 1, address not shift */

EIM_CS0GCR1 &= ~CSREC_BITS;
EIM_CS0GCR1 |= 2<<20; /*EIM_CS0GCR1 = 010, gap between same cs is 2 EIM clk*/

EIM_CS0WCR1 |= 0x0000ffff; /***********************/
return 0;
}

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