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LPC1768 GPIO state DURING reset

Question asked by Prakash Bhumireddy Employee on Aug 17, 2017
Latest reply on Aug 18, 2017 by Carlos_Mendoza



Our customer (Honeywell) has designed a product where "during" reset (not after reset), the GPIOs are settling to a high voltage (towards the Vdd/supply), due to which the interfaces are enabled accidentally "during" reset. They designed the application assuming the GPIO reset state is High-Z input.


Although, we have not reviewed their schematic and the actual environment, they would like to know the GPIO pin state 

"DURING" reset ( Is it High-Z, input with pull-up/pull-down etc?). Also would like to know the on-chip pull-up resistance/current value if the GPIO reset state is input with pull-up.


They need this information to calculate the external pull-up/down resistor/current in order to avoid inadvertent activation of interfaces DURING reset.


I tried to get the answer myself through communities, reference manual/datasheets, but no mention of this data.


This question should preferably go to the I/O designer of LPC1768 and kindly request to answer in relation to LPC1768.