AnsweredAssumed Answered

i.MX 6Solo timing between DQS and DQ

Question asked by Roman Rudenko on Aug 16, 2017
Latest reply on Aug 16, 2017 by igorpadykov

Hello NXP!


I need to know t1 and t2 timings, I was trying to find this information in JESD79-3D standart and I couldn't do it. I need DQS out to earliest valid DQ/DM time in writing cycle and DQS out to latest valid DQ/DM time in writing cycle. Can you give me this timings? I have i.MX 6Solo controller (partnumber: MCIMX6S7CVM08AC). DDR3l-800 (AC160/DC90).